1. Field of the Invention
The present invention relates to a bias voltage generating circuit, and particularly to a bias voltage generating circuit for generating a voltage higher than a power supply voltage or lower than the ground voltage and a semiconductor integrated circuit device incorporating therein the bias voltage generating circuit.
2. Description of Related Art
Recently, in order to reduce the power consumption of semiconductor integrated circuit, efforts have been made to lower the voltage level of power supply. As the voltage level of power supply decreases, the absolute value of a threshold voltage of MOS transistor gradually decreases. However, since increase in power consumption during a standby mode needs to be suppressed, an extent to which the threshold voltage of MOS transistor is lowered is forced to become smaller than that to which the voltage level of power supply is lowered. Particularly, in Dynamic Random-Access Memory (DRAM), to maintain a desired hold time for data latch, it is not desirable to reduce the threshold voltage of a transistor within a memory cell unit. However, when the voltage level of power supply is lowered and yet the threshold voltage is maintained at the same level as that used before the voltage level of power supply is lowered, a rate at which DRAM operates cannot be made higher. Accordingly, for example, a technique for supplying a voltage higher than a power supply voltage to a part of DRAM, such as a drive circuit for a word line, in order to make DRAM operate at a higher rate is employed.
FIG. 1 is a circuit diagram illustrating a bias voltage generating circuit disclosed in Japanese Patent Application Laid-open No. 9-106675 (1997). The conventional bias voltage generating circuit includes: an N-channel MOS transistor NT11 having a drain and a gate connected to a power terminal VCC for supplying a specific positive voltage and a backgate connected to ground; an N-channel MOS transistor NT12 having a drain and a gate connected to the power terminal VCC and a backgate connected to ground; an N-channel MOS transistor NT13 having a drain connected to the source of the N-channel MOS transistor NT11 via the interconnect line 61, a gate connected to the source of the N-channel MOS transistor NT12 via the interconnect line 62, a source connected to a bias voltage output terminal VOUT, and a backgate connected to a ground terminal GND; a capacitive element C11 having one end connected to the source of the N-channel MOS transistor NT11 via the interconnect line 61; and a capacitive element C12 having one end connected to the source of the N-channel MOS transistor NT12 via the interconnect line 62. Note that a capacitive element C0 is provided to stabilize a bias-voltage output from the bias voltage generating circuit.
The bias voltage generating circuit shown in FIG. 1 increases or boosts a voltage to a desired voltage level in the following manner. That is, an original clock signal CLK is configured to alternately have high levels and low levels at a specific time interval and the original clock signal is modified to present a clock signal having an amplitude corresponding to a difference between a potential at the power terminal VCC and ground potential, and then, the clock signal is supplied to the other end of the capacitive element C11 and the other end of the capacitive element C12.
FIG. 2 is a timing diagram of how the bias voltage generating circuit operates. FIG. 2 illustrates how a bias voltage output from the circuit returns to its steady-state voltage when the bias voltage is increased to its steady-state voltage and then, for example, current flows from the bias voltage generating circuit to the outside upon selection of a word line, lowering the bias voltage.
Hereinafter, an electric potential (hereinafter, referred to simply as potential) at the power terminal VCC is simply denoted by VCC and a potential at the ground terminal GND is simply denoted by GND. Furthermore, assume that a threshold voltage is defined as Vt when the backgate voltage of N-channel MOS transistor is zero (i. e., a potential difference calculated by subtracting the potential at source from the potential at backgate is zero) and an increase to Vt in the threshold voltage is defined as xcex94V when the potential at backgate is lowered to xe2x88x92VCC relative to the potential at source (i. e., a potential difference calculated by subtracting the potential at source from the potential at backgate is xe2x88x92VCC).
Referring to FIG. 2, when the original clock signal CLK is at a low level, the potential of the interconnect line 61 is represented by VCCxe2x88x92(Vt+xcex94V) and likewise, the potential of the interconnect line 62 is represented by VCCxe2x88x92(Vt+xcex94V). In this case, the potential at a bias voltage output terminal VOUT is assumed to be lower than its steady-state voltage.
When the original clock signal CLK changes to a high level, the clock signal supplied to the other end of the capacitive element C11 rises from GND to VCC after a little time elapses from the moment the signal CLK changes and therefore, the potential of the interconnect line 61 increases up to 2.times.VCCxe2x88x92(Vt+xcex94V). Furthermore, since the clock signal supplied to the other end of the capacitive element C12 rises from GND to VCC, the potential of the interconnect line 62 also increases up to 2.times.VCCxe2x88x92(Vt+xcex94V), turning the N-channel MOS transistor NT13 to an ON-state.
When the N-channel MOS transistor NT13 becomes turned on, since an electric charge in the interconnect line 61 moves to the bias voltage output terminal VOUT via the N-channel MOS transistor NT13, the potential at the bias voltage output terminal VOUT increases up to the potential of the interconnect line 61 less the threshold voltage (Vt+xcex94V) of the N-channel MOS transistor NT13, i. e., 2.times.VCCxe2x88x922.times.(Vt+xcex94V), and the potential of the interconnect line 61 decreases down to 2.times.VCC2.times.(Vt+xcex94V).
When the original clock signal CLK changes back to a low level, the clock signal supplied to the other end of the capacitive element C1 decreases from VCC to GND after a little time elapses from the moment the signal CLK changes and therefore, the potential of the interconnect line 62 decreases down to VCCxe2x88x92(Vt+xcex94V). Furthermore, although the clock signal supplied to the other end of the capacitive element C12 decreases from VCC to GND and accordingly, the potential of the interconnect line 62 once decreases down to VCCxe2x88x922.times.(Vt+xcex94V), the potential of the interconnect line 62 is charged by the N-channel MOS transistor NT12 and then returns to VCCxe2x88x92(Vt+xcex94V).
When current does not flow from the bias voltage generating circuit to the outside, the potential at the bias voltage output terminal VOUT keeps its steady-state potential, i. e., 2.times.VCCxe2x88x922.times.(Vt+xcex94V). When current flows from the bias voltage generating circuit to the outside and then the potential at the bias voltage output terminal VOUT becomes lower than its steady-state potential, the potential at the bias voltage output terminal VOUT again returns to 2.times.VCCxe2x88x922.times.(Vt+xcex94V) at the moment the subsequent original clock signal CLK changes to a high level, as is explained in the aforementioned description.
As described above, the conventional bias voltage generating circuit shown in FIG. 1 is able to generate a bias voltage of 2.times.VCCxe2x88x922.times.(Vt+xcex94V) in its steady-state condition. However, a power supply voltage has increasingly been lowered and in contrast, a threshold voltage inevitably has been gently lowered, as is already described. Accordingly, a difference between a bias voltage generated by the conventional bias voltage generating circuit and a power supply voltage is becoming smaller, eliminating beneficial effects produced by increase in bias voltage. This causes a strong need for a bias voltage generating circuit capable of generating a higher bias voltage.
Moreover, in some cases, a bias voltage generating circuit for generating a negative voltage potential lower than ground potential is employed and a threshold voltage of a MOS transistor having a low threshold voltage is controlled by applying the negative voltage potential to the MOS transistor to reduce leakage current between source and drain of the MOS transistor during a standby mode. The bias voltage generating circuit employed in such an application needs to generate a large negative voltage.
The present invention has been conceived in consideration of the above-described requirements and is directed to a bias voltage generating circuit that is configured to generate a bias voltage higher than a power supply voltage and improved to be able to generate a bias voltage higher than what is achieved when employing a conventional technique, or is directed to a bias voltage generating circuit that is configured to generate a bias voltage lower than a ground voltage and improved to be able to generate a bias voltage lower than what is achieved when employing a conventional technique.
A bias voltage generating circuit according to the first aspect of the present invention comprises:
a first power terminal for receiving a first voltage from outside;
a second power terminal for receiving a second voltage from outside;
a bias voltage output terminal for outputting a bias voltage to the outside;
a first MOS transistor having a drain and a gate connected to the first power terminal and a backgate connected to the second power terminal;
a second MOS transistor having a drain connected to the first power terminal, a gate connected to the source of the first MOS transistor, and a backgate connected to the second power terminal;
a third MOS transistor having a drain connected to the first power terminal, a gate connected to the source of the first MOS transistor, and a backgate connected to the second power terminal;
a fourth MOS transistor having a drain connected to the first power terminal, a gate connected to the source of the second MOS transistor, and a backgate connected to the second power terminal;
a fifth MOS transistor having a drain connected to the source of the third MOS transistor, a gate connected to the source of the fourth MOS transistor, a source connected to the bias voltage output terminal, and a backgate connected to the first power terminal;
a first capacitive element having one end connected to the source of the first MOS transistor and the other end for receiving a first clock signal;
a second capacitive element having one end connected to the source of the second MOS transistor and the other end for receiving a second clock having a phase opposite to that of the first clock signal;
a third capacitive element having one end connected to the source of the third MOS transistor and the other end for receiving a third clock signal; and
a fourth capacitive element having one end connected to the source of the fourth MOS transistor and the other end for receiving a fourth clock signal.
A bias voltage generating circuit according to the second aspect of the present invention comprises:
a first power terminal for receiving a first voltage from outside;
a second power terminal for receiving a second voltage from outside;
a bias voltage output terminal for outputting a bias voltage to the outside;
a first MOS transistor having a drain and a gate connected to the first power terminal and a backgate connected to the second power terminal;
a second MOS transistor having a drain connected to the first power terminal, a gate connected to the source of the first MOS transistor, and a backgate connected to the second power terminal;
a third MOS transistor having a drain connected to the first power terminal, a gate connected to the source of the first MOS transistor, and a backgate connected to the second power terminal;
a fourth MOS transistor having a drain connected to the first power terminal, a gate connected to the source of the second MOS transistor, and a backgate connected to the second power terminal;
a fifth MOS transistor having a drain connected to the source of the third MOS transistor, a gate connected to the source of the fourth MOS transistor, a source connected to the bias voltage output terminal;
a sixth MOS transistor having a drain connected to the first power terminal, a gate connected to the source of the second MOS transistor, a source connected to a backgate of the fifth MOS transistor, and a backgate connected to the second power terminal;
a seventh MOS transistor having a drain connected to the source of the third MOS transistor, a gate connected to the source of the second MOS transistor, a source connected to the backgate of the fifth MOS transistor, and a backgate connected to the second power terminal;
an eighth MOS transistor having a drain connected to the source of the fifth MOS transistor, a gate connected to the source of the third MOS transistor, a source connected to the backgate of the fifth MOS transistor, and a backgate connected to the second power terminal;
a first capacitive element having one end connected to the source of the first MOS transistor and the other end for receiving a first clock signal;
a second capacitive element having one end connected to the source of the second MOS transistor and the other end for receiving a second clock having a phase opposite to that of the first clock signal;
a third capacitive element having one end connected to the source of the third MOS transistor and the other end for receiving a third clock signal; and
a fourth capacitive element having one end connected to the source of the fourth MOS transistor and the other end for receiving a fourth clock signal.
A semiconductor integrated circuit device according to the third aspect of the present invention comprises a bias voltage generating circuit, in which the bias voltage generating circuit includes:
a power terminal for receiving a specific positive voltage;
a ground terminal for receiving a ground voltage;
a bias voltage output terminal for outputting a bias voltage;
a first N-channel MOS transistor having a drain and a gate connected to the power terminal and a backgate connected to the ground terminal;
a second N-channel MOS transistor having a drain connected to the power terminal, a gate connected to the source of the first N-channel MOS transistor, and a backgate connected to the ground terminal;
a third N-channel MOS transistor having a drain connected to the power terminal, a gate connected to the source of the first N-channel MOS transistor, and a backgate connected to the ground terminal;
a fourth N-channel MOS transistor having a drain connected to the power terminal, a gate connected to the source of the second N-channel MOS transistor, and a backgate connected to the ground terminal;
a fifth N-channel MOS transistor having a drain connected to the source of the third N-channel MOS transistor, a gate connected to the source of the fourth N-channel MOS transistor, a source connected to the bias voltage output terminal;
a sixth N-channel MOS transistor having a drain connected to the power terminal, a gate connected to the source of the second N-channel MOS transistor, a source connected to a backgate of the fifth N-channel MOS transistor, and a backgate connected to the ground terminal;
a seventh N-channel MOS transistor having a drain connected to the source of the third N-channel MOS transistor, a gate connected to the source of the second N-channel MOS transistor, a source connected to the backgate of the fifth N-channel MOS transistor, and a backgate connected to the ground terminal; and
an eighth N-channel MOS transistor having a drain connected to the source of the fifth N-channel MOS transistor, a gate connected to the source of the third N-channel MOS transistor, a source connected to the backgate of the fifth N-channel MOS transistor, and a backgate connected to the ground terminal.
The aforementioned objects, other objects associated therewith and features of the invention will be apparent from the following detailed description with reference to the attached drawings and from new matters disclosed in the claims.